Design of CI-BCH encoder and decoder integrated circuits


Аuthors

Volkov A. S.*, Solodkov A. V.**, Zaharow I. A.***

National Research University of Electronic Technology, 1, sq. Shokina, Moscow, Zelenograd, 124498, Russia

*e-mail: leshvol@mail.ru
**e-mail: solodkov_aw@mail.ru
***e-mail: wanueschok@mail.ru

Abstract

This paper describes the development of CI-BCH (Continuously Interleaved BCH) encoder and decoder integrated circuits for high-performance data transmission systems. A Verilog description of the encoder and decoder was developed, standard-cell synthesis was performed, and the integrated circuit topology was synthesized. The key parameters of the developed integrated circuit are 30,000 and 150,000 standard cells for the encoder and decoder, respectively, a clock frequency of up to 100 MHz, and a throughput of 1.6 Gbps. It is demonstrated that the developed decoder has low hardware complexity and can be integrated into systems-on-chip (SoC).

Keywords:

CI-BCH, encoder, decoder, FEC, Verilog, standard cells, topology

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